1. Field of the Invention
The present invention relates to a method of manufacturing a device.
2. Description of the Related Art
Conventionally, a pillar-type transistor (vertical transistor) has been used as a transistor having a small occupied area and suited for miniaturization. In this pillar-type transistor, diffusion layers to serve as a source and a drain are formed in the top portion of a pillar and in the semiconductor substrate around the pillar. In addition, a channel is formed between the source and the drain within the pillar.
JP2008-311641A discloses a method of manufacturing this pillar-type transistor. In the method disclosed in JP2008-311641A, a silicon substrate is first processed into a columnar (pillar-like) shape. A bottom diffusion layer is formed in a semiconductor substrate under and lateral to the pillar, a gate electrode is formed over a side surface of the pillar with interposed a gate insulating film therebetween. A top diffusion layer to serve as an LDD region is formed in a top portion of the pillar. Then, silicon is selectively and epitaxially grown on an exposed surface of the top portion of the pillar, in order to further form a top diffusion layer. Thereafter, a high-concentration impurity is introduced into the epitaxially-grown layer by an ion implantation method. The pillar-type transistor is thus formed (see paragraph [0053] and FIGS. 25 and 26).
In the method disclosed in JP2008-311641A, however, the thickness of the epitaxially-grown layer varies in some cases, depending on the growth conditions thereof. In addition, an impurity to be introduced in subsequent ion implantation reaches to the pillar portions (LDD region and channel region) in a thinned portion of the epitaxially-grown layer. This has been a cause for fluctuations or variations in transistor characteristics.
In a pillar-type transistor in particular, the characteristic fluctuations or variations of the transistor have been notable, compared with those of a planar transistor. That is, in the planar transistor, a source and a drain are formed in a substrate, and an epitaxial growth method is not used. Accordingly, the planar transistor has been free from such problems as film thickness fluctuations due to epitaxial growth. In addition, a channel is formed in a direction parallel to the principal surface of the substrate. Accordingly, even if any variations in the ion implantation of an impurity in a depth direction of the substrate occur, the effect of such variations on transistor characteristics has been minor. In contrast, in a pillar-type transistor, a channel is formed in a direction perpendicular to the principal surface of a substrate. Accordingly, any variations in ion implantation have had a major effect on transistor characteristics.